1. Field of the Invention
The invention relates to a method for testing a nonvolatile memory such as a flash memory which outputs a completion signal upon completion of a writing operation or an erasing operation in the memory.
2. Description of the Related Art
A flash memory employs a field-effect transistor with a floating gate as a memory device to write and erase data by accumulating an electrical charge to the floating gate and by discharging the accumulated electrical charge from the floating gate. Since the electrical charge in the insulated floating gate is retained even after a power source is disconnected, the flash memory is referred to as a nonvolatile memory. One example of the flash memory is disclosed in Japanese Patent Kokai No. 2000-40389.
The flash memory includes a control circuit which performs page-by-page writing of the data, e.g. 512 bytes in one page, and block-by-block erasing of the data, e.g. 32 pages in one block. Due to property inherent in the memory device, it is impossible to perform a high speed rewriting operation that is realized by a memory with a flip-flop. Accordingly, the writing data in one page is once stored in a buffer of the control circuit, and then the data is written to a “page” in a memory cell. Until the writing operation to the page is completed, not only a writing operation to the next page but also a data transfer operation to the buffer is prohibited.
FIGS. 2A and 2B of the accompanying drawing illustrate a conventional test method for a flash memory. Specifically, FIG. 2A is a diagram illustrating the test method, and FIG. 2B is a signal waveform chart during a writing test.
As shown in FIG. 2A, a flash memory 1 to be tested includes a control terminal section CON, an address terminal section ADDR, bidirectional data terminals DQ1-DQ7, and a multifunctional terminal DQ8/BUSY. The control terminal section CON has a plurality of terminals for receiving control signals such as a chip selection signal /CE, an output control signal /OE, and a writing control signal /WE, where ‘/’ denotes an inversion logic. The address terminal section ADDR has a plurality of terminals. The number of the terminals corresponds to the number of bits of address signals, which respectively designate addresses in a memory area such that whole memory area is covered by the address signals. In this instance, a block number and a page number are designated by a higher address signal AY, while an address within the page is designated by a lower address signal AX.
When one address is composed of 8 bits (1 byte) data, the bidirectional data terminals DQ1-DQ7 receive and supply data corresponding to the first through the seventh bits. The multifunctional terminal DQ8/BUSY sequentially receives writing data corresponding to the eighth bit during the data writing operation. After the completion of the receiving the whole writing data in one page, the multifunctional terminal DQ8/BUSY supplies a busy signal BUSY indicating a state of non-receiving the next writing data until the completion of the writing operation to actual memory cells.
On the other hand, a test apparatus 2 includes not only the control terminal section CON and the address terminal section ADDR which are similar to those of the flash memory 1, but also a plurality of multipurpose input and output terminals IOi (i=1 to n). The control terminal section CON outputs the control signals such as the chip selection signal /CE, the output control signal /OE and the writing control signal /WE, while the address terminal section ADDR outputs the address signals AX and AY. These control signals and address signals are supplied to the flash memory 1 in accordance with a test program incorporated in the test apparatus 2. It should be noted that the control terminal section CON and the address terminal section ADDR may be configured by the multipurpose input and output terminals IOi.
The input and output terminals IOi can be switched to be either input terminals or output terminals in accordance with the test program incorporated in the test apparatus 2. When the input and output terminal IOi of the test apparatus 2 is used as input terminals for receiving data from the flash memory 1, the input and output terminal IOi establishes a strobe condition such as a load timing of the data or a rise or a fall timing of the input signal.
The control terminal section CON and the address terminal section ADDR of the test apparatus 2 are respectively connected to those of the flash memory 1 via a test device provided therebetween. The input and output terminals IO1-IO7 of the test apparatus 2 are respectively connected to the data terminals DQ1-DQ7 of the flash memory 1. The input and output terminal IO8 of the test apparatus 2 is connected to the multifunctional terminal DQ8/BUSY of the flash memory 1.
A test operation will be hereinafter described.
As shown in FIG. 2B, as soon as a writing test is started, a write control signal /WE from the test apparatus 2 shifts from an ‘H’ level to an ‘L’ level. The ‘L’ level of write control signal /WE remains until the whole writing data in one page is output. On the other hand, the output control signal /OE to the flash memory 1 is always kept at an ‘H’ level. The input and output terminals IO1-IO8 of the test apparatus 2 are designated as output modes.
An address of the data to be written is then designated by the address signals AX and AY from the test apparatus 2. In this instance, a block number and a page number are designated by the address signal AY, while a top address, i.e., Address 0, of the page concerned is designated by the address signal AX.
Subsequent to the outputting of the address signals AX and AY, writing data D0 to be written into this address (that is AX=0) is output from the input and output terminals IO1-IO8 of the test apparatus 2. At the same time, the chip selection signal /CE from the test apparatus 2 shifts from an ‘H’ level to an ‘L’ level. Accordingly, the writing data D0 is introduced into the buffer within the flash memory 1.
When a predetermined time period elapses, the outputting of the address signals AX and AY is stopped, and the chip selection signal /CE shifts from the ‘L’ level to the ‘H’ level.
The address signal AX then designates the next address, i.e., Address 1. Subsequent to the outputting of the address signal AX, writing data D1 to be written into this address is output from the input and output terminals IO1-IO8 of the test apparatus 2. At the same time, the chip selection signal /CE from the test apparatus 2 shifts from the ‘H’ level to the ‘L’ level. Accordingly, the writing data D1 is introduced into the buffer within the flash memory 1. When a predetermined time period elapses, the outputting of the address signal AX is stopped, and the chip selection signal /CE shifts from the ‘L’ level to the ‘H’ level.
In a similar manner as describe above, the writing data are sequentially output up to the last address of the page concerned, i.e., Address 511.
The write control signal /WE from the test apparatus 2 then shifts to the ‘H’ level. The input and output terminal IO8 of the test apparatus 2 is switched to an input mode, and the strobe condition is established in order to detect the input signal shifting from the ‘H’ level to the ‘L’ level.
When the one-page-worth of writing data introduced in the buffer is written to the actual memory cell in the flash memory 1, the busy signal BUSY supplied from the multifunctional terminal DQ8/BUSY of the flash memory 1 shifts from the ‘H’ level to the ‘L’ level so that a completion of the writing is notified to the test apparatus 2. Consequently, the test apparatus 2 starts outputting writing data of the next page.
The above-described test method for the flash memory has the following problems;
(1) The input and output terminal IO8 of the test apparatus 2 needs an alternate switching operation between outputting of the writing data and inputting of the busy signal even during the writing test. Further, the writing test is immediately followed by a reading test in this test method, but a strobe condition of the reading test is different from that of the writing test. Accordingly, a test program for the test apparatus 2 becomes complicated and a programming and a debugging step therefor become time consuming, thereby prolonging a period for a development of the devices such as the flash memory 1.
(2) In a test apparatus having an ALPG (Algorithmic Pattern Generator), data with a specific pattern is output from the input and output terminal IOi and is written to a memory, and then the data which is read from the memory is compared with the specific pattern. When such test apparatus is used for the test of the flash memory 1 in a manner shown in FIG. 2A, the test apparatus can not make a correct determination because the input and output terminals IO8 receives the data DQ8 and the busy signal BUSY in a time-division manner. Accordingly, it is impossible to perform a writing operation and a reading operation consecutively in a single test.
(3) There is a test apparatus having a plurality of test circuits each compatible with a certain number of bits, e.g., 8 bits, such that the same test can be simultaneously performed for a plurality of flash memories. When such test apparatus is used to test a flash memory with 16 bits, two test circuits are necessary for a single flash memory, but the flash memory has only one multifunction terminal DQ16/BUSY. Consequently, use of merely two sets of the test circuits each having a configuration shown in FIG. 2A can not test the 16-bit flash memory.
(4) A test apparatus has a certain maximum operation frequency, and thus it is impossible to perform a high speed performance test with a frequency higher than the maximum operation frequency by means of a conventional measurement method. On the other hand, there is a test apparatus capable of performing a technique called pin-multiplex, in which two input and output terminals IOi is made to be a pair, and the clocks thereof are respectively distributed to a first half clock and a last half clock within a cycle so that a clock with pseudo doubled frequency is output. Use of such technique, however, causes such problems that the same data are always issued from the paired input and output terminals IOi, and the same decision procedures for expected values are established in the reading test. Accordingly, since only one input and output terminal IOi is not enough to monitor the busy signal BUSY, no flash memory can be tested by merely using the pin-multiplex in a manner shown in FIG. 2A.